Synchronous Complementary Metal Oxide Semiconductor (CMOS) logic circuits are commonly designed according to a Level Sensitive Scan Design (LSSD) technique. These LSSD circuits are responsive to a combination of a C clock signal and a B clock signal. The C clock signal and the B clock signal are non-overlapping. More specifically although they are of the same frequency it is a requirement of LSSD that active periods of the two clock signals do not coincide. A register in the logic circuit, designed according to an LSSD technique, consists of an array of Shift Register Latches (SRLs). An SRL consists of a first latch responsive to the C clock signal and a second latch responsive to the B clock signal. When the C clock signal is true, an input data bit is stored in the first latch. When the B clock signal is true, the input data bit is passed from the first latch and stored in the second latch. For the purpose of explanation, and to highlight aspects of the present invention, a process by which a latch responds to a clock signal by storing a data bit shall hereinafter be referred to as clocking.
Many synchronous logic circuits include a large number of multiple bit registers and may therefore contain thousands of SRLs. Power consumption problems can arise if such a logic circuit is manufactured by integrating CMOS devices on a silicon substrate. Logic gates consisting of CMOS devices consume most electrical power whilst in transience between logical states. This power is dissipated as heat. Therefore, the power consumed by many thousands of CMOS SRLs, switching on every clock cycle, makes a significant contribution to heat dissipated by a logic circuit. Such heat dissipation can restrict the choice of packaging material for encapsulating the logic circuit to those material with suitable heatsinking properties, which may not be the cheapest materials available. Therefore, since there is a demand for denser device integration and faster clock rates, to increase on-chip processing power, the need has arisen to examine methods for reducing power consumption associated with CMOS device technology.
Some synchronous logic circuits include registers for storing dependent data groups such as "set-up" parameters. Such data groups are modified infrequently during normal operation of the logic circuit. When such a data group changes, an address word, associated with the data group, can be generated by combinatorial logic in the logic circuit. The address word can be further decoded by the combinatorial logic to produce a true state in an I/0 address line which is otherwise held false. In a similar fashion, other I/0 address lines can be associated with other data groups stored in other registers in the synchronous logic circuit. In one such known synchronous logic circuit design, a separate suppression gate corresponds to every register storing a dependent data group. The suppression gate prevents the C clock signal from clocking the first latches of a register unless an associated I/0 address line is true. Such a function is referred to in the art as a gating function. This arrangement has the advantage that the use of C clock suppression can reduce the complexity of addressing logic and therefore the cost of combinatorial logic in the logic circuit. Furthermore, C clock suppression also provides some reduction in power consumed by the logic circuit. However, while the C clock signal to a particular register may be inhibited, because a corresponding I/0 address line is false, the B clock signal continues to clock the second latches in the register thereby causing unnecessary power consumption.